2d Threshold and Tran Conductance to Drain Current Ratio Modeling of Triple Material Double Gate (TMDG) Mosfet

VLSI technology is constantly evolving towards smaller line widths. In this paper analytical modeling for triple material double gate (TMDG) MOSFETs has been presented in the field of VLSI technology. An entire circuit is manufactured in a single piece of silicon. The level of integration of silicon technology as measured in terms of number of devices per IC. This leads to the concept of scaling in MOSFET devices. And further MOSFET occupies much smaller area of silicon than the equivalent BJT, due to which MOSFET requires less current and less power than its bipolar counterpart. SCALING enhances the design or manufacturing of extremely small complex circuitry using modified semiconductor material.The miniaturisation is achieved through scaling in two ways – size reduction of the individual devices and increase in the chip or dice size. But eventually scaling leads to short channel effects(SCEs). So, the main objective of our project is to reduce the short channel effects (SCEs) and threshold voltage roll off by using triple material double gate MOSFET (TMDG) in which the gate is made of three materials with different work functions. The 2D Poisson’s equation is solved for surface potential threshold voltage and electric field using parabolic approximation method and the work is extended to obtain transconductance for TMDG. Future work of our paper is extended to solve above mentioned parameters using Superposition method.